Can someone experienced in this space explain this to me in mid-tier engineering terms? Are chiplets physically connected chips that come from different wafers? Or are they designs that can be ‘dragged and dropped’? If they’re physically connected (pre-packaging? Post-packaging?) how is this different than putting them on a board with interconnects?

If it’s design-level, and tapeout needs to happen for a given chiplet design, why does the article mention different process nodes? And also, how is this different than any fabs available IP?

Thanks!

Intel has such a strong lead here, with Foveros doing stacked chips including ram (since the amazing, under-rated Lakefield), and with really good EIMB.

AMD is pretty famous for multi-chip, but they're only recently starting to do actually advanced integrating like Sea-of-Wires between chips. So far most of their chips have had big hot PHY to send data back & forth, rather than trying to make multiple chips that really can communicate directly with each other.

Interesting days ahead. The computer is on the chip now. A smaller domain of system building, with many of the same trade-offs & design challenges that it took to build a box.