Assembly Hall of Shame

173 points - today at 6:01 PM

Source

Comments

monocasa today at 9:08 PM
It says in the rules

> Trapped/emulated/virtualized instructions may only time the trap, not the handler.

But I feel like that 12ms write to an ACPI IO port at current leaderboard position 8 is probably trapping to SMM and being handled there.

Retr0id today at 7:35 PM
Related, and linked in the readme: https://github.com/xoreaxeaxeax/smiiiiiiiiiiiiiiii (using the slow instructions to break SMI)
layer8 today at 7:31 PM
Nop should be #1, because it is infinitely slow for what it does. ;)
TomatoCo today at 6:46 PM
This author also has other things like: A compiler that emits only `mov` instructions and another compiler that deliberately messes with the control flow so that, if disassembled, common debuggers will draw symbols like skulls or threats. https://github.com/xoreaxeaxeax/repsych
michalsustr today at 7:44 PM
Very cool! Also, huh interesting. I’ve used rdtsc to measure cycle diffs but had no idea its execution takes that long. Is that common across architectures?
markus_zhang today at 8:52 PM
Does that mean Chris Domas is ready for his next adventure?
metadat today at 6:47 PM
It’s crazy how computers still seem to get perceivably slow every few years, given how many instructions can be executed in 1ms. Shameful, even..

What’s that law called about programmers wasting all the compute on abstraction?

spoocecow today at 7:19 PM
Oh wow, glad to see Chris Domas active online again!
codeshaunted today at 6:48 PM
what im seeing from this chart is that we should be using the nop instruction for everything
vardump today at 6:33 PM
A great resource for any performance deoptimization.
IshKebab today at 8:29 PM
Using MMIO is cheating and makes the results very boring.

It would be much more interesting to know the results if you're only allowed to use main memory.

achierius today at 6:49 PM
It'd be really interesting to see whether the winning (losing?) instructions/strategies would be different on other architectures. At least right now the top spot (`fxrstor64` on MMIO, starve PCIe) seems relatively architecture-independent, but maybe something about MMIO ordering rules on e.g. POWER would be different enough to change that -- or perhaps open up new avenues?

I wonder what the actual limit on this `fxrstor64` is right now. If you can stall the PCIe bus for that long, then why not indefinitely? Certainly there's no forward progress guarantee here.

arn3n today at 6:45 PM
There’s definitely strategies here; A lot of the floating point operations use subnormals, and a lot of the worst instructions are slowed down by really, really fucking with MMIO.
2_foos_in_a_bar today at 6:37 PM
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