I've started to dabble in this only very recently. I have two iCEBreaker boards [0] in the mail right now that I'm excited for.

From what I understand, one of the big advantages of the up5k chip (the same chip on the webfpga and the icebreaker) is that there's an open toolchain that runs in seconds (at this chip size), which is not the case in the closed/Vivado/"typical fpga" part of the world. (feel free to correct me)

Purely in simulation this week, I had Claude (Fable) design a working Tetris out of 1400 relays - originally, this was for a Minivac web simulator that I/Fable had built [1]. Then, it compiled the relay netlist to Verilog and ran it on the simulated chip, comparing this (bezerk) port relay-for-relay against the original simulator. All matching (total llm time: less than an hour). I had it also make a viz of the netlist blinking through one simulated run [2] - sort of like visual6502.org..!

Today, I (Fable) ported tinystories [3], a very small language model to this exact same chip. It's currently "golfing" to get it to fit onto the real, not simulated chip (it's ~10% over, I'm hopeful). EDIT: it just golfed it! ~~9 tokens/sec!

None of these are "use cases", but these boards seem small/cheap enough that you can do new deranged things with them, which is very very exciting to me. I see a great future.

[0] https://1bitsquared.com/products/icebreaker

[1] https://minivac.greg.technology/tetris/

[2] https://necessary-doom-48128.ondis.co/

[3] https://arxiv.org/abs/2305.07759

WebFPGA

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